The present invention relates to a lateral heterojunction bipolar transistor and to a method of fabricating the same. More particularly, it relates to a lateral heterojunction bipolar transistor having a heterostructure such as Si/Si1-xGex or Si/Si1-x-yGexCy formed on an insulating substrate such as SOI (Silicon on Insulator).
There has conventionally been proposed technology for providing a transistor with excellent characteristics by forming a CMOS device and a bipolar transistor on a SOI (Silicon on Insulator) substrate composed of a silicon layer stacked on an insulating layer to lower the operating voltage of the transistor, provide a complete isolation between devices, and reduce a parasitic capacitance. In transmitting/receiving portions of a communication device handling an RF signal, in particular, a crosstalk between an analog circuit and a digital circuit presents a problem. However, the use of the SOI substrate holds promise of removing the crosstalk more drastically than the conventional technology.
On the other hand, a heterojunction bipolar transistor using a heterostructure such as Si/SiGe has been used commercially in recent years as a device operable in a region of RF frequencies, which has been considered difficult to fabricate by using the technology using a silicon process. Compared with a Si homojunction bipolar transistor, the heterojunction bipolar transistor has an excellent characteristic such that the resistance of a base can be reduced by adjusting the impurity concentration in the base to be higher than in the Si homojunction bipolar transistor since reverse injection of carriers from the base to an emitter is suppressed by using the heterostructure in which the band gap of the base is smaller than the band gap of the emitter.
In response to the system-on-chip demand made in recent years, BiCMOS technology has been requested to form a CMOS device and a bipolar transistor on a single chip. To form the bipolar transistor on a SOI substrate, however, it is necessary to increase the thickness of a silicon layer to a certain degree in a conventional vertical bipolar transistor structure, while it is necessary to reduce the thickness of the silicon layer in the CMOS device for high-speed operation and the suppression of a leakage current. However, the provision of a silicon layer having different thicknesses in a CMOS device region and a bipolar transistor region increases the complexity of the fabrication process.
To use a silicon layer having the same thickness in the bipolar transistor region as in the CMOS device region, there has been proposed the formation of a lateral heterojunction bipolar transistor on a SOI substrate. By using a lateral heterojunction bipolar transistor structure, the silicon layer having the same thickness in the both regions can be used and the process steps are greatly reduced in number. It has also been reported that a parasitic resistance is smaller in the lateral heterojunction bipolar transistor structure than in the vertical bipolar transistor formed by using a SOI substrate, which is advantageous in terms of high-speed operation.
FIGS. 10(a) and 10(b) are a plan view and a cross-sectional view of a lateral heterojunction bipolar transistor provided on a SOI disclosed in a document about an example of a prototype of such a lateral heterojunction bipolar transistor (A 31 GHz fmax Lateral BJT on SOI Using Self-Aligned External Base Formation Technology: T. Shino et. al. 1998 IEEE). As shown in the drawings, the lateral heterojunction bipolar transistor is formed on a SOI substrate including a BOX layer 1001 composed of a silicon oxide film and a silicon layer 1009. By using the SOI substrate, a parasitic capacitance in the operating region of the transistor can be reduced. The thickness of the silicon layer 1009 is 0.1 xcexcm. The silicon layer 1009 comprises: a strip-like p-type internal base layer 1004 doped with boron (B); two external base layers 1006 connected to the shorter side portions on both ends of the internal base layer 1004 and doped with boron (B) at a concentration higher than that in the internal base layer 1004; and an n-type emitter 1005 and an n-type collector 1002 disposed with the longer side portions of the internal base layer 1004 interposed therebetween. The emitter 1005 has been doped with arsenic (As) at a high concentration and the collector 1002 has been doped with arsenic at a non-uniform concentration. In short, the collector 1002 has a retrograde structure in which the concentration of arsenic is lower for an increased breakdown voltage in the portions thereof closer to the internal base layer 1004 and the external base layers 1006, which increases gradually with distance from the internal base layer 1004 and the external base layers 1006. The respective electrode formation portions of the external base layers 1006, the emitter 1005, and the collector 1002 are located on the respective outward tips of the regions such that the longest possible distances are provided therebetween and that parasitic capacitances among base electrodes, an emitter electrode, and a collector electrode are reduced. The foregoing document reports that such a lateral heterojunction bipolar transistor has provided a maximum oscillation frequency fmax of 31 GHz.
FIGS. 11(a) to 11(e) are perspective views illustrating a method of fabricating the bipolar transistor disclosed in the document.
First, in the step shown in FIG. 11(a), an oxide film and a SiN film (not shown) are formed on the n-type silicon layer 1009 into which phosphorus (P) has been introduced. Then, an array-like resist mask 1108 is formed on the SiN to cover an NPN active region. Subsequently, boron (B) is ion implanted at a dose of 4xc3x971015 atomsxc2x7cmxe2x88x922 into the silicon layer 1009 except for the NPN active region 1107 from above the resist mask 1108, whereby a P+ diffused region is formed. Next, in the step shown in FIG. 11(b), the SiN film is patterned by using the resist mask 1108 as a mask and side etched to form a SiN mask 1110, which is inwardly offset by about 0.2 xcexcm from the ends of the resist mask 1108. Thereafter, the resist mask 1108 is removed. Then, in the step shown in FIG. 11(c), a TEOS mask 1111 is formed in crossing relation to the SiN mask 1110. Subsequently, boron (B) is ion implanted at a dose of 1xc3x971014 atomsxc2x7cmxe2x88x922 and an acceleration energy of 25 keV into the silicon layer 1009 except for the region covered with the SiN mask 1110 and the TEOS mask 1111. Next, in the step shown in FIG. 11(d), the SiN mask 1110 and the TEOS mask 1111 are removed. At this time, the width of the internal base layer 1004 is determined by the diffusion distance traveled by implanted boron, which is measured from the end portion of the TEOS mask 1111. Finally, in the step shown in FIG. 11(e), portions serving as the emitter and the collector are mesa etched and arsenic (As) is ion implanted into the respective portions at a dose of 1xc3x971015 atomsxc2x7cmxe2x88x922 and an acceleration voltage of 120 keV and at a dose of 1xc3x971015 atomsxc2x7cmxe2x88x922 and an acceleration voltage of 65 keV. Since the silicon layer 1009 is amorphized by the ion implantations, it is recrystallized by RTA performed at 1050xc2x0 C. for 20 sec and by electric furnace annealing performed at 850xc2x0 C. for 60 sec.
By the foregoing process, a lateral bipolar transistor with a small parasitic capacitance which is high in fmax and operable at a high speed can be formed.
However, since the width of the internal base 1104 is determined by the diffusion distance of boron in accordance with the prior art technology disclosed in the foregoing document, it is difficult to constantly obtain a desired impurity distribution. Since the range in which the emitter 1105 and the collector 1102 are formed is determined by the diffusion distance of the n-type impurity, it is also difficult to form a pn junction with a sharp impurity concentration distribution.
It is therefore an object of the present invention to provide, during the formation of a lateral heterojunction bipolar transistor on a SOI substrate, means for accurately adjusting the width of an internal base layer or the like to a desired dimension and thereby provide a lateral heterojunction bipolar transistor having stable characteristics and a fabrication method therefor.
A first lateral heterojunction bipolar transistor comprises: a substrate having an insulating layer; a first semiconductor layer in a mesa configuration disposed on the insulating layer; a second semiconductor layer formed by epitaxial growth on a side surface of the first semiconductor layer, the second semiconductor layer having a band gap different from a band gap of the first semiconductor layer; and a third semiconductor layer formed by epitaxial growth on a side surface of the second semiconductor layer, the third semiconductor layer having a band gap different from the band gap of the second semiconductor layer, at least a part of the second semiconductor layer functioning as an internal base layer of a second conductivity type.
In the arrangement, the lateral thickness of the second semiconductor layer serving as the internal base layer is determined by epitaxial growth, not by the implantation of impurity ions. Consequently, the lateral thickness of the internal base layer is controlled with high accuracy. Since the internal base layer is formed by epitaxial growth, not by the implantation of impurity ions, the internal base layer can be doped in situ with an impurity, while it is laterally grown. This provides a sharp impurity concentration distribution in which impurity diffusion is suppressed.
There can be adopted a structure in which least the first semiconductor layer functions as a collector of a first conductivity type and at least a part of the third semiconductor layer functions as an emitter operating region of the first conductivity type.
The first lateral heterojunction bipolar transistor further comprises an external base layer of the second conductivity type in contact with the second semiconductor layer. The arrangement allows easy formation of an electrode.
The band gap of the second semiconductor layer is smaller than the band gap of the third semiconductor layer. The arrangement suppresses reverse injection of carriers from the second semiconductor layer functioning as the internal base layer into the third semiconductor layer functioning as the emitter operating region. As a result, base resistance can be reduced by adjusting an impurity concentration in the second semiconductor layer higher than a concentration in a homojunction bipolar transistor.
Each of the first and third semiconductor layers is composed of a silicon layer and the second semiconductor layer is composed of an alloy containing at least any two of Si, Ge, and C. The arrangement allows the formation of a heterojunction bipolar transistor in which impurity diffusion is suppressed by using a silicon process.
A principal surface of the first semiconductor layer is a {110} plane and a side surface of the first semiconductor layer in contact with the second semiconductor layer is a {111} plane. The arrangement provides the first semiconductor layer with a smooth side surface by using wet etching.
A first method of fabricating a lateral heterojunction bipolar transistor comprises the steps of: (a) forming an etching mask on a semiconductor layer disposed on an insulating layer to compose a substrate; (b) patterning the semiconductor layer by etching including dry etching and using the etching mask to form a first semiconductor layer in a mesa configuration; (c) epitaxially growing, on at least one side surface of the first semiconductor layer, a second semiconductor layer having a band gap different from a band gap of the first semiconductor layer; and (d) epitaxially growing, on a side surface of the second semiconductor layer, a third semiconductor layer having a band gap different from the band gap of the second semiconductor layer, at least the first semiconductor layer functioning as a collector of a first conductivity type, at least a part of the second semiconductor layer functioning as an internal base layer of a second conductivity type, at least a part of the third semiconductor layer functioning as an emitter operating region of the first conductivity type.
In accordance with the method, the lateral thickness of the first semiconductor layer functioning as the internal base layer is determined by epitaxial growth, not by the implantation of impurity ions. Consequently, the lateral thickness of the internal base layer is controlled with high accuracy. Since the internal base layer is formed by epitaxial growth, not by the implantation of impurity ions, the internal base layer can be doped in situ with an impurity, while it is laterally grown. This provides a sharp impurity concentration diffusion in which impurity diffusion is suppressed.
The step (b) includes: patterning the semiconductor layer by dry etching into a configuration of the etching mask and; forming the first semiconductor layer by performing wet etching with respect to a side portion of the patterned semiconductor layer, while leaving the etching mask. The arrangement is preferred since it removes etching damage, while retaining a high patterning accuracy.
The first method further comprises, after the step (d), the steps of: (e) depositing a polycrystalline semiconductor film on the substrate; and (f) planarizing the polycrystalline semiconductor film by CMP to form an emitter in contact with at least the third semiconductor layer. This allows easy formation of a low-resistance emitter adjacent the emitter operating region.
The first method further comprises, in or after the step (e), the step of: (g) introducing an impurity of the first conductivity type into a first region of the polycrystalline semiconductor film and introducing an impurity of the second conductivity type into a second region of the polycrystalline semiconductor film; and removing, of the polycrystalline semiconductor film, at least a portion located between the first and second regions to form an emitter in contact with the third semiconductor layer from the first region and form an external base layer in contact with the second semiconductor layer from the second region. This allows easy formation of a low-resistance emitter and a low-resistance external base layer by using a polycrystalline film such as a polysilicon film.
Preferably, the introduction of the impurity is performed by ion implantation using a mask.
Preferably, the step (g) is performed by wet etching.
The etching mask is formed by using a semiconductor layer having a principal surface of a {110} plane as the semiconductor layer on the insulating layer in the step (a) and such that the side surface of the first semiconductor layer in contact with the second semiconductor layer is a {111} plane in the step (b). This allows the formation of an internal base layer having a uniform lateral thickness by using a {111} plane which is etched at a particularly low speed and provides a smooth flat surface.
Preferably, the step (b) includes: crystal anisotropic etching using an etching solution containing at least any one of ethylenediamine, pyrocatechol, KOH, and hydrazine.
A second lateral heterojunction bipolar transistor disposed on an insulating layer comprises: a first semiconductor layer functioning as a collector; a second semiconductor layer disposed in contact with at least one side surface of the first semiconductor layer to function as an internal base having a band gap smaller than a band gap of the first semiconductor layer; a third semiconductor layer disposed in contact with a side surface of the second semiconductor layer to function as an emitter having a band gap larger than the band gap of the second semiconductor layer; first and second electrodes in contact with respective side surfaces of the first and third semiconductor layers; and a third electrode disposed in contact with a top surface of the second semiconductor layer.
This provides a lateral heterojunction bipolar transistor having a relatively simple structure and excellent characteristics of low parasitic capacitance, low parasitic resistance, and low base resistance, which is formed on the insulating layer.
Each of the first and second electrodes is composed of a metal. This particularly lowers the resistances of the emitter and collector.
A second method of fabricating a lateral heterojunction bipolar transistor comprises the steps of: (a) introducing an impurity of a first conductivity type into a first semiconductor layer containing an impurity of the first conductivity type, the first semiconductor layer being disposed on an insulating layer to compose a substrate; (b) forming, on the first semiconductor layer, an etching mask having a slit with a width of 200 nm or less; (c) removing a portion of the semiconductor layer located under the slit by etching using the etching mask to form a groove penetrating the first semiconductor layer; (d) epitaxially growing, from both side surfaces of the groove in the first semiconductor layer, a second semiconductor layer having a band gap different from a band gap of the first semiconductor layer such that the second semiconductor layer is buried in the groove; (e) forming openings in respective regions of the insulating layer located on both sides of the slit and above the first semiconductor layer; (f) performing wet etching with respect to the first semiconductor layer from the openings in the insulating layer to form hollow portions and leave respective portions of the first semiconductor layer on both sides of the second semiconductor layer; (g) forming first and second electrodes to be buried in the respective hollow portions; and (h) forming a third electrode to be buried in the slit in the insulating film in contact relation with the second semiconductor layer, the respective portions of the first semiconductor layer left on both sides of the second semiconductor layer functioning as a collector and an emitter operating region, the second semiconductor layer functioning as an internal base layer.
The method provides a lateral heterojunction bipolar transistor having a relatively simple structure and excellent characteristics of low parasitic capacitance, low parasitic resistance, and low base resistance, which is formed on the insulating layer.
Preferably, the step (f) includes: crystal anisotropic etching using at least any one of ethylenediamine, pyrocatechol, KOH, and hydrazine.
The step (a) includes a first ion implantation for implanting impurity ions of the first conductivity into the first semiconductor layer and a second ion implantation for implanting, into a portion of the first semiconductor layer, the impurity ions at a concentration higher than in the first ion implantation, the collector is formed from a portion of the first semiconductor layer with respect to which only the first ion implantation has been performed and the second ion implantation has not been performed, and the emitter operating region is formed from the portion of the first semiconductor layer with respect to which the first and second ion implantations have been performed. This allows respective impurity concentrations in the emitter operating region and in the collector to be adjusted optimally for the operation of the bipolar transistor.
A silicon layer is used as the first semiconductor layer and an alloy containing at least any two of Si, Ge, and C is used as the second semiconductor layer. This allows the fabrication of a lateral heterojunction bipolar transistor using a silicon process.